1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly, to a transistor having low-resistance metal source and drain structures which are vertically displaced from a channel, and to a method for producing this device.
2. Description of the Relevant Art
Advances in computer technology, among other factors, result in a continual demand for faster integrated circuits. Integrated circuit speed may be limited by various factors, such as circuit architecture, interconnection delays, and speed limitations of individual transistors. Such transistor speed limitations may often be described in terms of RC time constants, where R and C are resistance and capacitance, respectively, associated with the transistor structure. RC time constants characterize the time needed for a transistor to turn on or off, so that transistor speed may be increased by making RC time constants as low as possible. One type of resistance associated with a transistor structure is series resistance, or resistance encountered by carriers traveling within a given portion of the transistor, such as the source of a MOSFET. Contact resistance, the resistance associated with a contact to a transistor region, is another type.
Both series and contact resistance are associated with source, drain, and gate regions of MOS transistors. Series resistance is related to the resistivity of the doped silicon typically used for source, drain and gate regions, while contact resistance is related to the resistance of the junction formed between such a silicon source, drain or gate region and an interconnect, which is typically formed from metal. A partial cross-sectional view of a conventional MOSFET structure is shown in FIG. 1. Gate dielectric 12 and polysilicon gate conductor 14 are formed upon silicon substrate 10 by deposition and patterning of dielectric and polysilicon layers. Source 16 and drain 18 are of opposite carrier type than substrate 10. No patterning step is needed for introduction of source 16 and drain 18, since these impurity distributions are typically introduced after formation of gate conductor 14. Gate conductor 14 serves as a mask to exclude the dopants forming source 16 and drain 18 from the transistor channel underlying gate dielectric 12. Because photolithography and the associated alignment process is not used in forming source 16 and drain 18, the source and drain arc said to be "self-aligned" to the gate. The transistor and the fabrication method used to form it are also often described as self-aligned.
Self-aligned source/drain regions such as regions 16 and 18 in FIG. 1 exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that can increase RC time constants and limit high-frequency transistor performance. In addition, the self-alignment process allows smaller feature sizes to be used, because the size tolerances which must be left to allow for lithographic alignment error are not needed. The use of conventional self-aligned processes does impose limitations upon transistor fabrication, however. For example, the use of impurity regions in the semiconductor substrate to form the source and drain necessitates high-temperature (greater than about 900.degree. C.) processing to activate impurities and anneal substrate damage, if the source and drain impurities are introduced by ion implantation (as is generally the case). Alternative impurity introduction methods such as diffusion also involve high-temperature processes. The choice of gate materials is therefore limited, because the gate must be able to withstand the high-temperature source/drain processing. In part for this reason, the current material of choice for gate conductors in MOSFET fabrication is polycrystalline silicon, or polysilicon. The resistivity of a polysilicon gate conductor is typically lowered by doping, which is often performed by ion implantation, using the same implants which dope the self-aligned source and drain.
Problems can arise with this doping, however, in part because of the different rates of dopant diffusion in polysilicon as opposed to single-crystal silicon. Although typical gate conductor thicknesses are greater than the depths of the shallow junctions required for source and drain regions in high-performance devices, diffusion rates along the grain boundaries of polycrystalline films can be on the order of one hundred times as fast as in single-crystal silicon. This can allow dopants in a polysilicon gate conductor to diffuse across the thin gate dielectric and into the underlying channel region during high-temperature processes such as implant anneals. Such diffusion can leave a region of low carrier concentration in the polysilicon directly above the gate dielectric, an occurrence often called the "polysilicon depletion effect". This region of the gate conductor adjacent to the gate dielectric therefore has a higher resistivity, and the resulting device performs as if it had an increased gate dielectric thickness. Effective doping of polysilicon gate regions is further complicated in CMOS devices because of differences in diffusion behavior of boron, the typical p-channel transistor dopant, and arsenic, the typical n-channel transistor dopant. Boron diffuses more rapidly in polysilicon than arsenic, which tends to segregate at grain boundaries. Adequate activation of arsenic impurities throughout the gate conductor of an n-channel device without causing excessive boron diffusion and polysilicon depletion effects in a p-channel device presents significant challenges.
A further challenge associated with conventional self-aligned transistor fabrication is the difficulty of forming source/drain junctions shallow enough that short-channel effects are minimized. As an example of a short-channel effect, for a given oxide thickness and substrate doping, threshold voltage V.sub.T tends to decrease as channel length decreases, for channel lengths smaller than about 2 microns. As used herein, a decrease in V.sub.T refers to a V.sub.T which becomes less positive or more negative in the case of an n-channel device, or a V.sub.T which becomes less negative or more positive in the case of a p-channel device. This decrease in V.sub.T occurs because the effect of the source and drain depletion regions on the charge controlled by the gate becomes increasingly important as channel length decreases. Depletion regions and an inversion layer for the MOSFET of FIG. 1, under biasing conditions such that the transistor is turned on, are shown in the transistor of FIG. 2. Before free charge in inversion region 70 is induced by a voltage applied to gate conductor 14, a depletion region 72 (having a boundary marked with a short-dashed line) is formed in substrate 10 below gate conductor 14. The threshold voltage V.sub.T which must be applied to gate 14 to turn on the transistor includes the voltage needed to establish depletion region 72 and that needed to induce the carriers in inversion region 70.
As shown in FIG. 2, parts of depletion region 72 are formed by drain depletion region 74 arising from the drain-to-substrate junction and source depletion region 76 arising from the source-to-substrate junction. Boundaries of source and drain depletion regions 76 and 74 are marked by long-dashed lines in FIG. 2. This leaves only the charge in shaded depletion region 78 to be induced by the gate voltage, which reduces the voltage needed to turn on the transistor as compared to that predicted using depletion region 72. For given doping levels and oxide thickness, V.sub.T decreases as the channel length decreases because the fraction of the depletion region under the channel which is contributed by the source and drain regions becomes larger with decreasing channel length. This reduction in threshold voltage is undesirable because it increases the subthreshold, or "off", current of the transistor.
A second short-channel effect related to encroachment of source/drain depletion regions into the vicinity of the channel is known as "punchthrough". Punchthrough refers to current flow between the source and drain by a path separate from that along the transistor channel. This current path is established by widening of the drain and source depletion regions under bias until the drain and source depletion regions merge, thereby creating a continuous electric field driving current through the merged depletion region. The punchthrough current path is deeper within the substrate than the intended transistor channel, typically at approximately the source/drain junction depth. Punchthrough is undesirable because punchthrough current is less directly controlled by the gate of the transistor, and may flow even when the transistor channel is turned off.
Both threshold voltage reduction and punchthrough may be alleviated by reducing the encroachment of the source/drain depletion regions into the vicinity of the channel. This depletion region encroachment may be reduced by decreasing the junction depths of the source and drain. The formation of shallow source and drain junctions is, however, rather difficult to accomplish in transistor devices which employ fast-diffusing species as the source/drain dopant. Due to their relatively high diffusivity, some dopant species, such as boron, can penetrate deeply into the substrate during processing subsequent to introduction. Also, advances in technology are required to make available low-energy ion implanters before low implant depths can be realized.
While reducing the junction depth provides protection against short-channel effects such as V.sub.T reduction and punchthrough, it also undesirably gives rise to increased resistance in the source and drain junctions. As the resistance in the source and drain junctions increases, the saturation drive current and the overall speed of the transistor may drop. Moreover, forming ohmic contacts to relatively shallow junctions has several drawbacks. A contact layer which consumes the underlying source and drain junctions is often used during contact formation. For example, a refractory metal may be deposited across the source and drain junctions and heated to promote a reaction between the metal and the silicon of the underlying substrate. As a result of the reaction, a low resistivity self-aligned silicide (i.e., salicide) may form upon the junctions. The silicide may completely consume relatively shallow junctions, penetrating into the substrate underneath the junctions, a phenomenon known as "junction spiking". Consequently, the junctions may exhibit large current leakage or become electrically shorted. Therefore, precautions must be taken to prevent excessive consumption, and hence junction spiking, of the shallow junctions during contact formation.
A gate conductor made from a low-resistance metal would alleviate many of the problems with polysilicon gate conductors discussed above. Unfortunately, low-resistance metals such as aluminum are not able to withstand the high-temperature processing needed, for example, to anneal the as-implanted source and drain regions employed within a standard self-aligned process. It would therefore be desirable to develop a method of forming self-aligned gates using low-resistance metals or metal alloys. The desired method should further provide low-resistance source and drain regions, and low-resistance contacts to source, drain and gate regions so that series and contact resistances associated with the resulting transistor are reduced. In addition, these low-resistance source and drain regions should have small junction depths, so that short-channel effects such as punchthrough and V.sub.T reduction are minimized.